Open Source Chips Movement (OSCM)
Grand Challenges in Open IC Design: Democratization of Chip Design
Round 2 registration is extended till 8th September 2024.
Contact us at support@makerchips.org for more information.
Join the grand challenge in any of the following categories
Round 2 classes will begin in November
Through this program, we offer a 4-month internship program with an opportunity for free chip fabrication.
Category 1: School Kids - 6th grade or above (No fee)
Category 2: BSc/BTech/MSc students (One-time registration fee of Rs.1000 or $12)
Category 3: MTech/PhD students (One-time registration fee of Rs.1000 or $12)
Category 4: Developers and industry professionals (Monthly registration fee of Rs.1000 or $12)
Online weekend classes
Online evening classes
Hands-on learning
Mentorship and support
Fabricate a working chip
Certification from IEEE
Available for the following microcourse
Digital IC Design
https://ml.ieee-cas.org/course/view.php?id=532
In this CASS MiLe microcourse, we will delve into the realm of ultra-reliable digital IC design, led by Professor Alex James from Digital University Kerala. This course will provide insights into designing digital integrated circuits that are both intelligent and highly dependable. Meticulously crafted to offer a comprehensive understanding of digital IC design techniques, this microcourse includes a one-hour lecture divided into smaller, easy-to-digest segments, ensuring a focused and effective learning experience.
You can register and complete the same to obtain the certificate.
Analog IC Design
https://ml.ieee-cas.org/course/view.php?id=530
In this CASS MiLe microcourse, we will delve into the realm of ultra-reliable analog circuit design Led by Professor Alex James from Digital University Kerala. this course will provide insights into designing analog circuits that are both intelligent and highly dependable. This microcourse has been meticulously crafted to offer a comprehensive understanding of analog circuit design techniques. The one-hour lecture is divided into smaller, easy-to-digest segments, ensuring a focused and effective learning experience
Welcome
Join and take part in the largest community driven open IC design challenges
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Digital chip design
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Analog circuits
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Mixed Signal Circuits
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RF circuits
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Neuromorphic circuits
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Signal Processing circuits
Create Talent in Chip Design With Free Chip Fabrication
Our vision is to create a large pool of chip design talent. Our initial targets are ambitious: to train a minimum of 1000 individuals in chip design. We aspire to foster a culture of entrepreneurship and nurture skilled circuit designers. Join us on this journey as we pioneer innovation and excellence in chip design at scale. Through this program, we aim to create a community of young chip designer natives who can become the next generation of makers and leaders.
The program is open to anyone around the world, in particular, we are interested to hear from those residing in developing and emerging countries.
Areas of training
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Digital chip design
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Analog circuits
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Mixed Signal Circuits
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RF circuits
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Neuromorphic circuits
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Signal Processing circuits
Outcomes
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New IPs
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Patents
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Publications
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Fabricated chips
Unlock the Fascinating World of Electronics and Chip Design
Welcome to our comprehensive guide on IC Design Flow, the systematic process that transforms concepts into integrated circuits (ICs) powering the technologies shaping our world. Whether you're a seasoned semiconductor professional or a curious enthusiast, this page serves as your gateway to understanding the intricate journey from initial concept to silicon reality. Here we delve into the world of open-source IC design tools and libraries.“The goal is to lower the barrier and access to silicon and allow the vibrant youthful intellects to push the limit of what can be done.”
Driving Semiconductor Evolution: The Significance of Open-Source IC Design
The trend of open-source technologies is making its way into the semiconductor industry. Open-source semiconductor chip design platform aligns with the growing interest in collaborative and community-driven approaches to hardware development.This page explores how these open source tools reshape the way designers innovate and create cutting-edge integrated circuits.
Providing open-source process design kits (PDKs), EDA tools, and foundational building blocks aims to enhance the accessibility of integrated circuit (IC) or chip design.
Getting started with Open Designs
When we look at IC design from a perspective angle, it's all about carefully arranging different parts of a circuit so they can work together to do specific jobs. Imagine putting together a puzzle where each piece has a special role to play. First, we need to decide what we want the puzzle to look like, or in IC design terms, what we want our chip to do. Then, we pick the right puzzle pieces, or circuit elements, to make it happen. These pieces need to fit together just right, like gears in a machine, to perform their tasks smoothly. Throughout this process, we need to keep in mind the limitations and requirements of what the chip will be used for. Ultimately, our goal is to create a chip that not only does its job well but also doesn't cost too much to make and can be produced efficiently.
While the specifics of IC design workflows can vary widely depending on factors like foundry, process, company, and individual preferences, they generally fall into four main domains:
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Digital: This domain focuses on designing ICs using transistors as switches and logic circuits. Digital IC design deals with processing binary data and implementing algorithms, often for tasks like computation, storage, and communication.
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Analog: Analog IC design involves working with real-world signals that haven't been digitized. It includes designing components such as amplifiers, filters, and voltage regulators, which are crucial for processing continuous signals like audio, video, and sensor data.
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RF (Radio Frequency): RF IC design is a specialized subset of analog design that deals specifically with signals at radio frequencies. It encompasses the design of components for wireless communication systems, such as antennas, amplifiers, and frequency synthesizers.
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Mixed-signal: Mixed-signal design combines elements of both digital and analog design to create integrated circuits that process both digital and analog signals. These ICs are common in applications such as data converters, sensor interfaces, and communication interfaces.
Each domain has its own set of design challenges, techniques, and methodologies. While digital design focuses on high-speed logic and optimization for power and area, analog design emphasizes precision, noise, and linearity. RF design requires specialized knowledge of electromagnetic theory and transmission line effects. Mixed-signal design integrates digital and analog circuits while managing their interactions and ensuring compatibility.
Overall, the IC design flow process may involve a combination of these domains, depending on the requirements of the project and the expertise of the design team.
Digital IC Design Flow
In semicustom digital ASIC design, a circuit is constructed by using a set of predefined logic components, known as standard cells. These cells are predesigned and their layouts are validated and tested by the foundry (or an specialized company). Standard-cell ASIC technology allows us to work at the gate level rather than at the transistor level and thus greatly simplifies the design process. The device manufactures usually provides a library of standard cells as the basic building blocks. The library normally consists of basic logic gates, simple combinational components (and-or inverters, multiplexers, full adders, etc.) and basic memory elements (D-type latch and flip-flop). Some libraries may also contain more sophisticated function blocks, such as an adder, barrel shifter, random access memory (RAM), etc.
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Design Specification: A concise functional and performance requirements of an integrated circuit (IC).
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High-level system design: Hardware Description Language (HDL) is a specialized programming language used to model and describe digital logic circuits and systems.It Involves Design Partition , Entry-Verilog Behavior Modeling, Simulation/Functional Verification, Integration and Verification.
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Logic Synthesis : Involves RTL(Register Transfer Level) description of the design into a netlist consisting of logic gates and flip-flops.
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Placement & Routing : Placement in IC design involves strategically positioning components and functional blocks on the chip's layout to optimize factors like signal integrity and area utilization. Routing involves establishing connections between these components through metal layers, ensuring efficient signal propagation while avoiding congestion and minimizing delay.
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Layout : IC level layout involves integrating all functional blocks onto the chip's layout, including cell placement, scan chain/clock tree insertion, and cell routing. It undergoes physical and electrical design rules checks, layout versus schematic verification, and parasitic extraction. Post-layout timing verification ensures timing requirements are met before GDSII creation and tape-out for fabrication.
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GDSII : A GDS file contains information about the geometric shapes, layers, and other physical properties of the components that make up an IC design. It's commonly used for transferring layout data between different electronic design automation (EDA) tools and for manufacturing masks used in the fabrication process.
Open-source Digital IC design tools
Behavioural Simulation Tools
Verification Tool
Synthesis Tool
RTL2GDS
Binary software distribution
Analog IC design Flow
Analog IC design and digital IC design follow distinct methodologies due to their inherent differences. While digital design operates largely at an abstract level, relying on automated processes for gate-level placement and routing, analog design demands a more personalized approach to each circuit, including detailed considerations of transistor sizing and configuration.
Analog design is predominantly a manual endeavor. It typically commences with the creation of a schematic diagram using a schematic editor. This schematic is then subjected to simulation using a SPICE-level simulator, with the resulting outputs scrutinized to ensure they meet performance criteria. If satisfactory, the next step involves the labor-intensive task of manually crafting the IC layout using a graphical layout editor. This layout is meticulously inspected to verify its accuracy and adherence to design specifications.
Open-source Analog IC design tools
Schematic Flow
Simulation
Physical Design
Netgen
open-source process design kits (PDKs)
Open-source process design kits (PDKs) refers to the kits containing a set of files, libraries, and documentation that are openly available and provide essential information and resources for designing integrated circuits (ICs) or chips. These kits typically include technology files, device models, layout rules, and other design parameters necessary for designing ICs using a specific semiconductor fabrication process. By being open-source, these PDKs promote accessibility, collaboration, and innovation in IC design by allowing designers to freely access, modify, and redistribute the design resources.
Open-source PDKs are available from various wafer foundries, including SkyWater Technology's SKY130 and GlobalFoundries' GF180MCU.
SkyWater SKY130 PDK
Open PDKs is distributed with files that support the Google/SkyWater sky130 open process description Here and also on GitHub github.com:google/skywater-pdk , you'll discover a plethora of valuable information about their available 130nm CMOS process.
Despite belonging to a mature node (which is quite distant from a leading nm-FinFET node), this process offers an extensive array of process options and features. It's perfectly suitable for numerous analog and digital designs, and even RF up to a few GHz.
SKY130 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry. The technology is the 8th generation SONOS technology node (130nm).
The technology stack consists of;
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5 levels of metal (p - penta)
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Inductor or Inductor-Capable (i)
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Poly resistor (r)
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SONOS shrunken cell (s)
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Supports 10V regulated supply (10R)
This document provides a concise overview of the different mask (GDS) layers, wiring resistance and capacitance, as well as electromigration regulations.
Unlock the Fascinating World of Electronics and Chip Design
Preparing an IC layout for production at a wafer foundry is an intricate process that involves several checks. Once all these checks are successfully completed and the layout, inclusive of pads, seal rings, etc., is finalized, it is forwarded to the foundry, typically in the form of GDS2 or OASIS files.
For the Makercass internship, we are leveraging the services provided by efabless, which offers infrastructure chips such as Caravel (for digital ICs) or Caravel Analog (for analog ICs). These chips come equipped with essential elements like pads, ESD protection, and programming infrastructure. This document provides initial guidance on utilizing these infrastructure chips for tape-out at efabless.
Given the significant cost and time involved in IC fabrication, it's crucial to ensure that the implemented design is error-free. Besides extensive simulation, a formal design review involving multiple engineers is conducted before tape-out. This review meticulously examines the design, layout, simulation results, and other critical aspects. The provided tape-out (TO) checklist consolidates essential considerations for this crucial stage.